The present invention relates to electrical circuits and more particularly to background calibration technique for pipelined analog-to-digital converters (ADCs).
Analog-to-digital conversion is the process of converting an analog data signal, which is most commonly represented as voltage, into a digital format. Determining a digital value which represents a particular analog input is known as xe2x80x9cquantizationxe2x80x9d. Serial, delta-sigma or oversampling, parallel, and pipelined are some of the many different analog-to-digital conversion architectures which exist. Different architectures are suited to different needs. Serial analog-to-digital architecture offers the widest range of performance in analog-to-digital conversion, from low power and low resolution to quantizations with very high resolutions. Basic serial architecture quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to fully quantize. Delta-sigma analog-to-digital architecture is used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed output. This process is also referred to as oversampling because more samples of the analog data are quantized than actually become output.
Parallel analog-to-digital architecture provides the fastest quantization rate per analog signal. In the parallel architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. Parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2Nxe2x88x921 comparators and 2Nxe2x88x921 resistors to achieve a digital value, with N bits of resolution, per cycle. Pipelined analog-to-digital architecture is a method of quantizing an analog signal in stages. Algorithms exist for obtaining one or more bits of resolution per stage. For example, in a 1.5-bit per stage converter, the digital output of each stage is either 1, 0, or xe2x88x921. One bit is resolved at each stage with the resulting analog residue passed along to the next stage for resolution of another bit. After a latency of N cycles, a single digital value for a single analog input is produced. Other methods are able to output more than 1-bit per stage, needing fewer latency cycles to produce a digital value with the same resolution. The use of pipelining permits a high degree of parallelism, so that one complete output per cycle can be produced after the pipeline fills up.
Pipelined ADCs have many applications. They are particularly useful when low voltage, high speed, high resolution quantization is required. The pipelined analog-to-digital conversion architecture""s ability to meet these demands makes it ideal for high volume telecommunications application such as various digital subscriber lines, digital signal processing at video rates, and for stand alone high speed analog-to-digital converters. The advantage of pipelined analog-to-digital conversion is that each stage of resolution is separated. Once the analog signal is resolved at the first stage and the result passed to the second stage, a new signal can be processed by the first stage. The passing of result and signal from stage to stage continues to stage N at which point a digital value of N bits of resolution can be produced. Quantization of the first signal to N bits of resolution is achieved in N cycles of latency.
However, because each stage resolves one bit and passes the result to the next stage, the former stage is free to resolve a bit of the next analog sample. This pipeline design allows N analog samples to be in the process of quantization simultaneously. Once the first analog sample is quantized, after N cycles, each successive analog sample is quantized one cycle later. Thus, a high throughput of one sample per cycle is achieved. Errors can be introduced into the conversion process at different stages by different components. The most common components in analog-to-digital conversion which can cause error are capacitors. Capacitors can introduce error because of a mismatch concerning the capacitance ratio of two or more capacitors used in sampling and amplifying an analog signal. In a conventional switched-capacitor pipelined ADC the accuracy is fundamentally limited by capacitor mismatch and finite amplifier gain.
Various self-calibration techniques have been proposed to address the capacitor mismatch induced by the digital to analog subconverter (DASC) and interstage gain error. Most of these techniques require the normal operation of the converters to be interrupted in order to perform the calibration. This can impose a burden on the user who decides when the converter can be interrupted and when the converter needs be recalibrated due to temperature or other environmental changes. A superior method is to use a background calibration technique whose operation is transparent to the user.
One method of background calibration is to employ an extra pipeline stage that is used to substitute the stage being calibrated. While the ADC is in normal operation, this extra stage is calibrated. One stage of the pipeline is then switched out for calibration while the extra calibrated stage is switched into the pipeline. The drawback with this approach is that in a well designed pipeline, the first few stages, which are the most critical, usually consume more power than later stages. Since the accuracy of the pipeline is determined by the accuracy of the first few stages, the extra stages added for calibration will consume significant amounts of power. In addition, this technique requires an additional successive approximation ADC to measure the error. Although the successive approximation ADC can be low power, it has to consume enough power to be fast enough to track temperature and other environmental changes. Another disadvantage of this technique is that it results in fixed pattern noise due to periodic substitution of stages. Another proposed background calibration scheme requires the addition of a calibration signal to the input. However, this results in a reduction of the useful dynamic range of the converter.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to systems and methods for calibrating a pipeline Analog-to-Digital Converter (ADC). The present invention employs a slow but accurate ADC or a slow but accurate ideal pipeline stage to correct for the residue errors in a non-ideal pipeline stage. The ideal pipeline stage samples the same input as the non-ideal pipeline stage and determines an ideal residue voltage based on the sampled input. An error function samples the actual residue voltage output and provides an initial residue voltage estimate. The error function maps the actual residue voltage to the ideal residue voltage to compensate for errors (e.g., capacitor mismatch, finite operation amplifier gain error, offsets, charge injection errors) associated with the pipeline stage. A correction algorithm is executed to optimize one or more parameters associated with the error function. The correction algorithm executes iteratively until the initial residue voltage estimate is approximately equal to the actual residue voltage. Upon optimization, the error function with the one or more optimized parameters can be applied to the pipeline stage to compensate for errors associated with the stage.
In one aspect of the invention, the correction algorithm is a gradient-descent least mean square (LMS) approach. A calibration technique that involves the use of a slow-but-accurate ADC in conjunction with an LMS algorithm to find parameters, which correct for the residue errors like finite op-amp gain error, capacitor ratio mismatch and charge injection error in a non-ideal pipeline stage result in a significant improvement in the integral nonlinearity (INL) and differential nonlinearity (DNL) of the ADC. The algorithm can be implemented in digital domain or in the analog domain. The present invention is applicable to a variety of different implementations. One such example is in the area of broadband networks, where a high resolution ADC at the front end enables complex signal processing to be done in the digital domain.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.